library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;


entity write_back is
generic (numBit : integer := 32);
port(	LOAD_in: in  std_logic_vector (numBit-1 downto 0);
		ALU_in : in  std_logic_vector (numBit-1 downto 0);
		sel 	 : in  std_logic;
		output : out std_logic_vector (numBit-1 downto 0)
);
end write_back;

architecture Structural of write_back is
component muxer is
generic (N : integer := 32);
port(	data_0 : in  std_logic_vector (N-1 downto 0);
		data_1 : in  std_logic_vector (N-1 downto 0);
		sel 	 : in  std_logic;
		output : out std_logic_vector (N-1 downto 0)
);
end component;
begin

MUX: muxer generic map(numBit) port
map ( data_0 	=> LOAD_in,
		data_1 	=> ALU_in,
		sel 		=> sel,
		output	=> output
);

end Structural;

